A Channel Decoder Implemented by CMOS Analog Circuits in Digital Communication System

摘要：

To realize low power channel decoder in digital communication system,basing on the a-posteriori probability algorithm,the paper fabricates an analog probability decoder of trellis code by using CMOS analog circuits.The decoding performance is given.When the SNR is over 4.8dB,for 950KHz input signal,the analog decoders BER is zero.If the input signal is 6MHz,the BER will be about 10-4.The highest speed of the decoder can be up to 20MHz.Simulation results also show that the analog decoder decreases at least one order of magnitude in power consumption and chip area at the same rate compared with the digital decoder.The design method is also suitable for implementing the analog decoders of Turbo code and LDPC code.

作者: Shuhui Yang Xuehua Li Yafei Wang

作者单位: College of Photoelectricity Information and Communication EngineeringBeijing Information Science and College of Photoelectricity Information and Communication Engineering Beijing Information Science an

会议类型: 国际会议

会议名称: 9th International Conference on Signal Processing(第九届国际信号处理学术会议)(ICSP08)

会议地点: 北京

会议语种:英文

在线出版日期: 2008-10-26（万方平台首次上网日期，不代表论文的发表时间）