An Efficient VLSI Architecture of Sub-pixel Interpolator for AVS Encoder

摘要：

Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter.In this paper,an efficient VLSI architecture of interpolation supporting AVS Baseline@L4 is presented.Vertical redundant data reuse,horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle.The separated 1-D interpolation filters are used to improve throughput and hardware utilization.The proposed design is implemented on the Vertex4 XC4VLX200 field programmable gate array with operating frequency of 150MHz and can support 1080p (1920×1080) 30fps AVS real-time encoder.It is a useful intellectual property design for real-time high definition video application.

关键词： AVS interpolation data reuse separated 1-D architecture

作者: Chen Guanghua Zhang xiaoli Liu Ming Zhu Jingming Ma Shiwei Zeng Weimin

作者单位: Key Laboratory of Advanced Display and System Applications,Ministry of Education & Microelectronic Research and Development Center,Shanghai University,Shanghai 200072,China

会议类型: 国际会议

会议名称: 9th International Conference on Signal Processing(第九届国际信号处理学术会议)(ICSP08)

会议地点: 北京

会议语种:英文

在线出版日期: 2008-10-26（万方平台首次上网日期，不代表论文的发表时间）