Efficient Wireless Digital Up Converters Design Using System Generator

摘要：

A WCDMA Digital Up Converter (DUC) design based on FPGA is presented.Aiming to shorten the design period and increase the design performance,a powerful design tool,Xilinx System Generator is used.The RRC filter and the Half-band filter are designed by using MATLAB FDATool,and implemented by using Xilinx FIR Compiler.The DDS module is generated by Xilinx DDS Compiler.Finally,the DUC design is implemented into Xilinx XC5VSX50T device.Using Vitex-5 DSP48E slices,the complex-multiplier speed reaches 368.64MHz.The simulation results show that the system design flow based on Xilinx System Generator is simple and feasible,and the productivity is increased.The performance meets the requirements for the downlink transmit path.

作者: Wang Wei Zeng Yifang Yan Yang

作者单位: School of Information & Communication Engineering,Tianjin Polytechnic University,Tianjin City,China,300160

会议类型: 国际会议

会议名称: 9th International Conference on Signal Processing(第九届国际信号处理学术会议)(ICSP08)

会议地点: 北京

会议语种:英文

在线出版日期: 2008-10-26（万方平台首次上网日期，不代表论文的发表时间）