VLSI Implementation of CAVLC Decoder with Power Optimized for H.264/AVC Video Decoding

摘要：

This paper presents an efficient method of the contest-based adaptive variable length code (CAVLC) decoder with power Optimized for H.264/AVC standard.In the proposed design,according to the regularity of the codewords,the first 1 detector is used to solve the problem that the traditional method of table-searching has low efficiency and high power dissipation.Considering the relevance of the data used in the process of RunBefores decoding,arithmetic operation is combined with FSM,which achieves higher decoding efficiency.According to the CAVLC decoding flow,clock gating is employed in module level and register level respectively,which reduce 43％ dynamic power dissipation.The proposed design can decode every syntax element in one clock cycle.When the proposed design is synthesized at clock constraint of 100MHz,the synthesis result shows that the design costs 11300 gates under a 0.25um CMOS technology,which meets the demand of real time decoding in H.264/AVC standard.

关键词： H.264/AVC CAVLC decoder

作者: Chen Guanghua Liu Ming Zhu Jingming Ma Shiwei Zeng Weimin

作者单位: Key Laboratory of Advanced Display and System Applications,Ministry of Education & Microelectronic Research and Development Center,Shanghai University,Shanghai 200072,China

会议类型: 国际会议

会议名称: 9th International Conference on Signal Processing(第九届国际信号处理学术会议)(ICSP08)

会议地点: 北京

会议语种:英文

在线出版日期: 2008-10-26（万方平台首次上网日期，不代表论文的发表时间）