Finding Tightly-coupled Sub-arrays on Reconfigurable Meshes

摘要：

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper　presents an algorithm to find a maximum logical array (MLA) that has　shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (k/2th) logical column and then makes it nearly straight for the MLA with k logical columns.A dynamic programming approach is presented to cpmpact other logical columns toward the middle logical column ,resulting in a tightly-coupled MLA.In addition,the lower bound of the interconnect length of the MLA is proposed.Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size ,according to theproposed lower bound.

关键词： Mesh reconfiguration processor array routing algorithm

作者: Wu Jigang Thambipillai Srikanthan Kai Wang

作者单位: Center of High Performance Embedded Systems,School of Computer Engineering,Nanyang Technological University,Singapore,639798

会议类型: 国际会议

会议名称: The Inaugural Symposium on Parallel Algorithms, Architectures and Programming(并行算法、结构和编程国际研讨会)

会议地点: 广州

会议语种:英文

页码: 19-36

在线出版日期: 2008-09-16（万方平台首次上网日期，不代表论文的发表时间）