The Design of a Cycle Accurate Multi-core Architecture Performance Simulator

摘要：

As multi-core technology has become the trend to improve the performance of processor,there is more need to design a performance simulator for the design of multicore architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator,it is a component design,which can be customized to different multi-core architectures,furthermore,provides a practical tool for the design and evaluation of multi-core architecture.

作者: Gang Wang Zhang Tiefei Like Yan Xie Bin Tianzhou Chen

作者单位: College of Computer Science,Zhejiang University,Hangzhou,Zhejiang,310027,China

会议类型: 国际会议

会议名称: The Fifth IEEE International Symposium on Embedded Computing(SEC 2008)(第五届IEEE国际嵌入式系统计算会议)

会议地点: 北京

会议语种:英文

页码: 282-287

在线出版日期: 2008-10-06（万方平台首次上网日期，不代表论文的发表时间）