Design of Heterogeneous Adders Based on Power-Delay Tradeoffs

摘要：

The performance of arithmetic adders varies widely in their power consumption,delay,and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder,the heterogeneous adder architecture is adopted. In heterogeneous adder architecture,a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each subadder. In this paper,a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bitwidth of each sub-addec.

作者: Sanghoon Kwak Dongsoo Har Jeong-Gun Lee Jeong-A Lee

作者单位: Department of Info.and Comm.GIST Gwangiu,Republic of Korea Department of Computer Engineering Hallym University Chunchun,Korea Department of Computer Engineering Chosun University Gwangju,Korea

会议类型: 国际会议

会议名称: The Fifth IEEE International Symposium on Embedded Computing(SEC 2008)(第五届IEEE国际嵌入式系统计算会议)

会议地点: 北京

会议语种:英文

页码: 223-226

在线出版日期: 2008-10-06（万方平台首次上网日期，不代表论文的发表时间）