Validation of ASIP Architecture Description

摘要：

Validation is one of the most complex and expensive tasks in current Application Specific Instruction Set Processors (ASIP) design process. Many existing approaches employ a multiple-level approach to efficiently design and verify ASIP design. This paper presents a novel extended timed Petri Net model called HDPN-Hardware Design based-on Petri Net to model systems at multiple levels,and introduces a verification scheme based on HDPN to satisfy the requirement of Design Space Exploration (DSE). This paper focuses on formal modeling and verification ASIP architecture.And a DLX pipelined processor is presented to demonstrate the validity and usage of this method.

作者: Yan-yan Gao Xi Li Jie Yu

作者单位: Dept.of Computer Science,University of Science and Technology of China,China;Embedded System Laborat School of Computer Engineering and Science,Shanghai University,Shanghai China

会议类型: 国际会议

会议名称: The Fifth IEEE International Symposium on Embedded Computing(SEC 2008)(第五届IEEE国际嵌入式系统计算会议)

会议地点: 北京

会议语种:英文

页码: 88-93

在线出版日期: 2008-10-06（万方平台首次上网日期，不代表论文的发表时间）