LUT-based FPGA Implementation of SMS4/AES/Camellia

摘要：

The FPGA performance of ciphers mainly includes area and throughput of implementation. In this design,several cryptographic algorithms such as SMS4,AES and Camellia have been implemented to analyze their performance and study the influence of the area with two different LUT-size FPGA devices. This paper uses VHDL to describe circuit function,choose Altera StratixⅡand Cyclone Ⅱdevices to simulation.Feedback structure is chosen to be the implementation structure,which can get balance between speed and area. The implementation results show that compared with 4-LUT of the Cyclone Ⅱ,the wider look-up tables(LUTs) in the ALMs of Stratix Ⅱ is more suitable for the encryption functions,and the SMS4 hardware cost is smallest,suitable for the Wireless local area network (WLAN) communication need.

关键词： SMS4 AES Camellia FPGA LUT VHDL

作者: Xianwei Gao Erhong Lu Li Li Kun Lang

作者单位: Beijing Electronic Science and Technology Institute,Beijing 100070,P.R China

会议类型: 国际会议

会议名称: The Fifth IEEE International Symposium on Embedded Computing(SEC 2008)(第五届IEEE国际嵌入式系统计算会议)

会议地点: 北京

会议语种:英文

页码: 73-76

在线出版日期: 2008-10-06（万方平台首次上网日期，不代表论文的发表时间）