Recognizing Geometric Path from Polygon-based Integrated Circuit Layout

摘要：

As the continual decrease of the feature size,The parasitic inductance and capacitance effect play important role in IC design and verification. Previous works on layout ex traction mainly concentrated on how to find out the type of devices and connections between them,few works has addressed the information of centerlines and widths of IC in-terconnects in a polygon-based VLSI layout,which are re-quired in inductance calculation and other applications. In this paper,an efficient scheme for the centerline-based path recognition from an IC mask layout is presented. Unlike the division-based methods,a tree-traverse-based approach is proposed. This new scheme can be realized as a reverse procedure of the layout generation from wire routing trees.Moreover,this scheme can handle complex all-angle wires.Experimental results show that this scheme has nearly lin-ear computational complexity yet generates precise results.

关键词： VLSI mask layout path recognition interconnect extraction

作者: Zhaohui Yuan Shilei Sun Gaofeng Wang

作者单位: School of Computer Science Institute of Microelectronics and Information Technology Wuhan university,Wuhan,430072,China

会议类型: 国际会议

会议名称: The Fifth IEEE International Symposium on Embedded Computing(SEC 2008)(第五届IEEE国际嵌入式系统计算会议)

会议地点: 北京

会议语种:英文

页码: 31-36

在线出版日期: 2008-10-06（万方平台首次上网日期，不代表论文的发表时间）