VLSI Design of Equalizer Using Pipelined Filter

摘要：

When a digital signal is transmitted over a typical bandlimited channel. noise and intersymbol interference often arise and are the main impairments to reliable communication,sometimes both with multipath and Doppler spread.A design of equalizer using pipeline technique is presented for the efficient equalization in high-speed communication over multipath channels with large delay spreads.In such terrible situation,the number of fiIter taps in equalizer may be up to 200 or more.The size and cost would be critical problem if we implement the equalizer in conventional method.To overcome the shortage,this paper proposes a VLSI design of equalizer with pipeline filter technique.The mapping results shows that the proposed design reduce nearly 50％ in size compared with the conventional equalizer.

关键词： Pipelined filter Large delay spreads isI Resource-sharing

作者: Lin Pingfen Peng Bei

会议类型: 国际会议

会议名称: The International Conference Information Computing and Automation(2007国际信息计算与自动化会议)

会议地点: 成都

会议语种:英文

页码: 795-798

在线出版日期: 2007-12-19（万方平台首次上网日期，不代表论文的发表时间）