Memory Models for an Application-Specific Instruction-set Processor Design Flow

摘要：

To optimize system performance for a specific target application,embedded system designers may add some new instructions,called Application-Specific Instructions (ASIs),by automatic design flow. In past days,most Application-Specific Instruction-Set Processor (ASIP) researches focus on reducing instruction latency to improve performance regardless of the impact of memory access. In this paper,a design flow is proposed to automatically generate ASIs and to compare the performance between considering register transferring and regardless of it. The experiment results show the proposed approach can achieve up to 14％ performance improvement and 10％ memory access reduction comparing to no register transferring consideration.

作者: Jiying Wu Chijie Lin Desheng Chen Yiwen Wang

作者单位: Department of Information Engineering and Computer Science Feng Chia University,Taichung,Taiwan

会议类型: 国际会议

会议名称: The 2008 International Conference on Embedded Software and Systems Symposia(ICESS 2008)(2008国际嵌入式系统及嵌入式软件会议)

会议地点: 成都

会议语种:英文

页码: 471-478

在线出版日期: 2008-01-01（万方平台首次上网日期，不代表论文的发表时间）