Performance Improvement using Application-Specific Instructions under Hardware Constraints

摘要：

An Application-Specific Instruction-set Processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance,cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper,a design flow is developed to automatically combine the disjoint operations as an ASI to enrich the selection varieties. The operation cover-ratio and the ASI latency model are used to select profitable ASIs so that the performance can be improved. The experimental results show the maximal 1.64x speed up can be obtained under hardware cost less than 8000 LEs in Altera FPGA.

作者: Chijie Lin Jiying Wu Jerung Shiu Chiuyun Hung Desheng Chen Yiwen Wang

作者单位: Department of Information Engineering and Computer Science,Feng Chia University Taichung,Taiwan

会议类型: 国际会议

会议名称: The 2008 International Conference on Embedded Software and Systems Symposia(ICESS 2008)(2008国际嵌入式系统及嵌入式软件会议)

会议地点: 成都

会议语种:英文

页码: 459-463

在线出版日期: 2008-01-01（万方平台首次上网日期，不代表论文的发表时间）