Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture
On transport triggered architectures (TTAs) featuring huge scheduling freedom,parallelism is exploited at not only operation level,but also data transportation level.Software pipelining,an aggressive compiler optimization scheme for exploiting instruction level parallelism across loop iterations,has been studied extensively. However,only few efforts were focused on software pipelining on TTAs.In these existing works,intuitive yet less efficient methods were used,namely either modulo scheduling algorithm with some heuristics or parallel language to implement software pipelining on TTA. We propose a new software pipelining method on TTAs in order to fully evaluate the scope of scheduling freedom of TTA and take advantage of it. In this paper,we formulate the problem of constructing a resource constrained rate-optimal software pipelining with minimal loop overhead on TTAs as an integer linear programming (ILP ) problem. The formulated problem is solved with GNU Linear Programming Kit (GLPK). We apply our approach to major loops in Livermore loop benchmarks. Comparing with the previous schedulers implemented with modulo scheduling algorithm,our ILP approach creates schedules which bring significant performance enhancement to applications on TTA.
Lei Jiang Yongxin Zhu Yipeng Wei
School of Microelectronics Shanghai Jiao Tong University
国际会议
成都
英文
451-458
2008-01-01（万方平台首次上网日期，不代表论文的发表时间）