Address Register Allocation in Digital Signal Processors

摘要：

It is important in signal processing to optimize a code inside loops. In most programs,addressing computation accounts for a large fraction of an execution time. From the fact that typical DSP programs access massive amounts of data,it is easy to conclude that handling addressing computation properly in DSP domain is a more important subject than in general purpose computing in order to achieve a compact code with real-time performance. In this paper,we develop an algorithm that can eliminate an explicit use of address register instructions in a loop and find a lower bound on the number of ARs by finding strongly connected components (SCCs) of an extended graph.

作者: Jinpyo Hong J. Ramanujam

作者单位: School of Intemet-Media Korea University of Technology and Education Cheonan,KOREA Dept.of Electrical and Computer Engineering Louisiana State University Baton Rouge,LA,USA

会议类型: 国际会议

会议名称: The 2008 International Conference on Embedded Software and Systems Symposia(ICESS 2008)(2008国际嵌入式系统及嵌入式软件会议)

会议地点: 成都

会议语种:英文

页码: 331-337

在线出版日期: 2008-01-01（万方平台首次上网日期，不代表论文的发表时间）