A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing
This paper presents a novel image interpolation method,extended linear interpolation,which is a lowcost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed Based on the approach,the low-cost hardware architecture with digital image scaling is designed under the real-time requirement.Our proposed method provides a simple hardware architecture design,low computation cost and is easy to implement. The presented architecture is implemented on the Virtex-lI FPGA,and the VLSI architecture has been successfully designed and implemented with TSMC 0.13μm standard cell library.The simulation results demonstrate that the high performance architecture of extended linear interpolation at 267MHz with 26200 gates in a 452×452μm2 chip is able to process digital image scaling for HDTV in real-time
Chung-chi Lin Ming-hwa Sheu Huann-keng Chiang Zeng-chuan Wu Jia-yi Tu Chia-hung Chen
Graduate School of Engineering Science and Technology Department of Electronic Engineering National Yunlin University of Science & Technology,Taiwan
国际会议
成都
英文
196-202
2008-01-01（万方平台首次上网日期，不代表论文的发表时间）