Energy Efficiency of Scratch-Pad Memory at 65 nm and Below:An Empirical Study
A number of approaches have been proposed so far for reducing the energy consumption of embedded systems by using scratch-pad memory. However,most of previous work focused on dynamic energy reduction,and did not take enough consideration of the leakage energy in their evaluations. As the technology scales down to the deep submicron domain,the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore,evaluation of energy consumption including the leakage energy is necessary. In this paper,we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65 nm,45 nm,and 32 nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling.
Energy consumption scratch-pad memory embedded systems deep submicron
Hideki Takase Hiroyuki Tomiyama Gang Zeng Hiroaki Takada
Graduate School of Information Science,Nagoya University Furo-cho,Chikusa-ku,Nagoya 464-8603,Japan
国际会议
成都
英文
93-97
2008-01-01（万方平台首次上网日期，不代表论文的发表时间）