A Novel Model for Variable Allocation on Memory-Bank of DSP

摘要：

Cooperation between CPU and memory is a key to improve efficiency of DSP application.There is an obvious gap between high speed of CPU and IOW memory band.width.New memory architecture had been invented to tackle the bottleneck Furthermore,HW/SW co-design is a useful way for this problem.especially in real-time and huge data digital signal processing area.In this paper,we address the variable allocation problem in parallel model,to maximize the benefit of memory-bank architectural fcature.We foCUS on a new graph model called data parallel allocation graph(DPAG)for the variable partitioning.Unlike the previous graph model,which is known as the interference graph(IG),our graph model can be used to analyze a cyclic DFG.After that,we provide a scheduling algorithm that based on DPAG model,it could dynamical ad iust the variable allocation to gain maximum parallel property.

关键词： memory-bank variable allocation parallelism DSP graph model

作者: Lei Zhang Jianping Li Weiwei Lv

会议类型: 国际会议

会议名称: The International Conference Information Computing and Automation(2007国际信息计算与自动化会议)

会议地点: 成都

会议语种:英文

页码: 51-55

在线出版日期: 2007-12-19（万方平台首次上网日期，不代表论文的发表时间）