High Performance All Digital Phase Locked Loop Mathematics Modeling And Design

摘要：

The paper introduces a novel architecture of all digital phase locked loop(ADPLL).It proposes a novel frequency acquisition method by separating frequency detecting process from phase detecting process which shortens the acquisition-time greatly.Furthermore,1-bit quantified theory is used in ADPLL to increase the controllability of the loop.A precise mathematical model of the ADPLL is built with Matlab.Through the simulation result,the feasibility of this system is justified.Stabilization is an important performance of PLL.The proposed ADPLL is a nonlinear system,so the conventional linear system analysis theory is not suit anymore.This paper uses Lyapunov theory to test stabilization of the proposed ADPLL system.

关键词： ADPLL mathematical models stabilization

作者: Jiancheng Li Tao Xu Zhaowen Zhuang Yongfeng Guan

作者单位: School of Electronic Science and Engineering,National University of Defense Technology,Changsha, P.R.China 410073

会议类型: 国际会议

会议名称: 2008 IEEE International Conference on Onformation and Automation(IEEE 信息与自动化国际会议)

会议地点: 张家界

会议语种:英文

页码: 1395-1399

在线出版日期: 2008-06-20（万方平台首次上网日期，不代表论文的发表时间）