FPGA Implementation of Digital Filter

摘要：

This paper introduces the basic knowledge of digital filter,and summing up the general design of digital filters,as well as some of the more efficient algodthms.Analysis of the advantages and disadvantages of various methods of design,the paper contends many kinds of structural plans.Then we focus on the CSD code which is used to achieve multiplier application.In this way,the hardware resources can be saved.And also,its quit a good way to increase the multipliers speed.

关键词： digital filter FPGA pipeline CSD code

作者: Fan Liu

作者单位: School of Information Technology,Jiangnan University,Wuxi,Jiangsu,214122,China

会议类型: 国际会议

会议名称: 2008年国际电子商务、工程及科学领域的分布式计算和应用学术研讨会(2008 International Symposium on Distributed Computing and Applications for Business Engineering and Science)

会议地点: 大连

会议语种:英文

页码: 1338-1341

在线出版日期: 2008-07-27（万方平台首次上网日期，不代表论文的发表时间）