Instruction Fetch Module Design of 32-bit RISC CPU Based on MIPS

摘要：

In this paper,we analyze MIPS instruction format、instruction data path、 decoder module function and design theory based on RISC CPUT instruction set.Furthermore,we design instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set.Function of IF module mainly includes fetch instruction and latch module、address arithmetic module、check validity of instruction module、synchronous control module.Function of IF modules are implemented by pipeline and simulated successfully on QuartusⅡ.

关键词： MIPS Data Flow Data Path Pipeline

作者: Yuehua Ding Kui Yi Ping Sun

作者单位: Department of Computer Science and Information Engineer,WuHan Polytechnic University,Wuhan,HuBei,430023,China

会议类型: 国际会议

会议名称: 2008年国际电子商务、工程及科学领域的分布式计算和应用学术研讨会(2008 International Symposium on Distributed Computing and Applications for Business Engineering and Science)

会议地点: 大连

会议语种:英文

页码: 1109-1116

在线出版日期: 2008-07-27（万方平台首次上网日期，不代表论文的发表时间）