Evaluating a Low-Power Dual-Core Architecture
With the rapid development of silicon technology, chip die size and clock frequency increase; it becomes very difficult to further increase the performance of silicon devices only by speeding up their clock. We believe a more practical way to increase their speed is to use the abundant transistor resource to implement several cores and make the cores execute in parallel. In the paper, we propose a processor-coprocessor architecture to increase the speed of the most frequently-used short program segments and reduce their power consumption. As these segments dominate the dynamic execution trace of embedded programs, the overall increment of performance and power-saving is significant. A dataflow coprocessor and a RISC coprocessor are implemented for comparison. The experimental results show the dataflow coprocessor is faster and more power-efficient than the other one, due to the fact that the dataflow coprocessor offers natural properties for fine-grained instruction-level parallel processing and its parallelism is self- scheduling. Except for data dependencies, there is no constrained sequentiality, so a dataflow program allows all forms of instruction parallelism.
Yijun Liu Pinghua Chen Guobo Xie Guangcong Liu Zhenkun Li
The Faculty of Computer Guangdong University of Technology Guangzhou, Guangdong, China, 510006
国际会议
7th International Symposium,APPT 2007(第7届高级并行处理技术大会)
广州
英文
80-89
2007-11-22（万方平台首次上网日期，不代表论文的发表时间）