The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction
Recent years, as the wide deployment of embedded and mobile devices, reducing the power consumption in order to extend the battery life becomes a major factor that a designer must consider when designing a new architecture. DVS is regarded as one of the most effective power reduction techniques. This paper focuses on run-time compiler driven DVS for power reduction, especially two key design issues including DVS analysis model and DVS decision algorithm. Based on the design framework presented in this work, we also implement a run-time DVS compiler which is fine- grained, adaptive to the programs running environment without changing its behavior. The obtained system is deployed in a real hardware platform. Experimental results, based on some benchmarks, show that with average 5％ performance loss, the benchmarks benefit with 26％ dynamic power savings and the energy delay product (EDP) improvement is 22％.
dynamic compiler DVS low power
Xiang LingXiang Huang JiangWei Sheng Weihua Chen TianZhou
College of Computer Science, ZheJiang University, Hangzhou 310027, China School of Electrical and Computer Engineering, Oklahoma State University, 202 Engineering South, Sti
国际会议
7th International Symposium,APPT 2007(第7届高级并行处理技术大会)
广州
英文
233-240
2007-11-22（万方平台首次上网日期，不代表论文的发表时间）