Architecture Research and Optimization for CABAC Decoder
Comparing with other video coding standard, H.264/AVC has better performance and higher efficiency, and it has been applied in many areas such as Steam Media, HDTV, teleconference, video storage, etc. Although CABAC can attain very high data compression ratio, it is realized at a cost of increasing complexity, and its decoding efficiency is not ideal also in current hardware implementation mode. Based on the CABAC arithmetic research and architecture analysis, this paper indicates the bottleneck in CABAC decoding process and presents a novel architecture of CABAC decoder which takes optimization design. The new storage mode is proposed to reduce the memory access frequency which greatly influences the decoding speed, and four decoding engines are concatenated to optimize the architecture. The experimental verification of the decoder in FPGA proved that optimizing architecture can improve efficiency remarkably and can meet the demand of real-time high level video communication.
Zhangjin Chen Feng Ran Meihua Xu Chen Jin
Computer Center;Shanghai University, Shanghai, 200072, P.R. China Microelectronic Research & Development Center;Shanghai University, Shanghai, 200072, P.R. China School of Mechanical Engineering and Automation;Shanghai University, Shanghai, 200072, P.R. China;Mi Microelectronic Research & Development Center Shanghai University, Shanghai, 200072, P.R. China
国际会议
南宁
英文
2007-07-20（万方平台首次上网日期，不代表论文的发表时间）