Design and Realization of Cascade Expansion Control Circuit in Asynchronous FIFO

摘要：

The storage capacity and data width of a single FIFO memory circuit are always limited, usually unable to meet all kinds of specific design requirements of complicated electrical system. So it needs to be parallel connected or cascaded to expand the capacity and data width according to the practical application. This paper presents a practical and simple FIFO memory expansion logic control method, the cascade logic control circuit has been designed, the working principle and circuit timing simulation waveform of the every control module has also been detailed analyzed. The design concepts and specific logic control circuits can also be used to design the cascade logic control circuit of other FIFO memory.

关键词： MAX113 Data Acquisition FPGA

作者: 姚莉 张超 刘文怡

作者单位: 中北大学电子测试技术国家重点实验室 太原山西 030051

会议类型: 国际会议

会议名称: 第六届中国国际纳米科技研讨会

会议地点: 成都

会议语种:英文

在线出版日期: 2007-11-19（万方平台首次上网日期，不代表论文的发表时间）