The Design for Testability of Longtium Microprocessor
Modern Microprocessor integrates many millions of transistors, with a deep on-chip pipeline of execution and embedded functions such as large register file and Cache, with a small number of test points, requires the additional design for testability, to simplify test pattern generation and decrease test complexity. Longtium microprocessor, which is compatible with x86 instruction system, is designed for embedded system. In order to reduce the cost for system integration, design for testability should be use in the design. This paper analyzes the structure of the microprocessor firstly, then analyzes the popular methods used in design for testability, and proposes built-in-self-test (BIST) should be used in the microprocessor. In the design, march-algorithm is used in testing cache, linear feedback shifter register is used in testing other logic module. Because Wallace multiplier is on the critical timing path in the microprocessor, the DFT circuit introduces more timing penalty. From analysis, it shows that a 32-bit MUX cause the timing cost. The location of the MUX is changed to optimize timing, whereas the function of the BIST circuit is not changed. With Design Compiler and TetraMax from Synopsys Inc, it is estimated that the BIST incurs only 4.2％ area overhead and 5.1％ timing overhead, whereas gets 98.4％ faulty coverage. This microprocessor is integrated into an SOC, which has been implemented with 0.18μm CMOS technology in SMIC successfully.
Wang Danghui Gao Deyuan Zhang Shengbing
Aviation Micro-Electronics Center, Northwestern Polytechnical University Xian, P.R.China
国际会议
北京
英文
2007-08-05（万方平台首次上网日期，不代表论文的发表时间）