A Multiple Faults Test Generation Algorithm Based on Neural Networks for Digital Circuits

摘要：

A multiple faults test generation algorithm based neural networks for digital circuits is proposed in this paper because the test generation for multiple faults in digital circuits is more difficult. This algorithm change multiple faults into single fault firstly and constructs the constraint network of the fault for the single fault circuit with method of neural networks. The test vectors for multiple faults in the original circuit can be obtained by solving the minimum of energy function of the constraint network for the fault with genetic algorithm method. The experimental results on some international standard circuits demonstrate the feasibility of the algorithm.

关键词： neural networks genetic algorithm constraint network energy function

作者: MENG Xiang HANG Zhigang ZHAO Ying QU Pingping

作者单位: Electrical & Information Engineering College, Beihua University, Jilin, 132021

会议类型: 国际会议

会议名称: 第七届国际测试技术研讨会

会议地点: 北京

会议语种:英文

在线出版日期: 2007-08-05（万方平台首次上网日期，不代表论文的发表时间）