An Effective Path Delay Fault Test Generation Algorithm for Digital Circuit

摘要：

An effective path delay fault test generation algorithm for digital circuit is proposed in this paper because of its importance. The digital circuit is transformed firstly a partial leaf-dag circuit using path-leaf transformation. Then we generate test vectors for stuck-at fault in the partial leaf-dag circuit using improved Boolean difference method. Finally we transform the test vectors into two-pattern tests vectors for path delay fault in the original digital circuit. The experimental results on some international standard circuits demonstrate the feasibility and the effectiveness of the algorithm.

关键词： path delay fault partial leaf-dag circuit stuck-at fault Boolean difference

作者: ZHAO Ying MENG Xiang HANG Zhigang QU Pingping

作者单位: Electrical &information Engineering College, Beihua University, Jilin, 132021

会议类型: 国际会议

会议名称: 第七届国际测试技术研讨会

会议地点: 北京

会议语种:英文

在线出版日期: 2007-08-05（万方平台首次上网日期，不代表论文的发表时间）