An Effective Method to Reduce Test Power Dissipation

摘要：

In order to reduce test power for scan operation, a scan cell and test vector reordering algorithm and corresponding hardware architecture is proposed in this paper. Experiments on ISCAS89 benchmark show that the proposed method is rather effective in reducing test power and the hardware overhead is reasonable acceptable.

关键词： scan cell reorder test vector reorder test power

作者: Yu Yang Peng Xiyuan

作者单位: Dept. of Automatic Test and Control, Harbin Institute of Technology Harbin, Heilongjiang 150001, China

会议类型: 国际会议

会议名称: 第七届国际测试技术研讨会

会议地点: 北京

会议语种:英文

在线出版日期: 2007-08-05（万方平台首次上网日期，不代表论文的发表时间）