FPGA-based hardware to achieve the stereoscopic display
This paper presents a simple and does not rely on computer operation systems to achieve time-division stereoscopic display system, uses Lattice XP series nonvolatile FPGA to achieve two-way video sampling, video synthesis and display, uses VHDL language to design and control clock signal, SDRAM controller, and video encoder and decoders C I 2 register for the allocation of the initialization. Achieve the alternative display of each frame of varied formats of two-way video. Adopt scheme that LCD switch plate and passive glasses to achieve stereoscopic display.
FPGA stereoscopic display stereo vision time division multiplexing single chip integration accelerometer gyroscope
ZHANG Guangwei AN Zhiyong ZHENG Fangyin ZHANG Weiwei
Changchun University of science and technology, Changchun, 130022,
国际会议
北京
英文
2007-08-05(万方平台首次上网日期,不代表论文的发表时间)