Image Matching Algorithms on Embedded Vision System Using FPGA
Field Programmable Gate Arrays (FPGAs) have been an attractive option for improving the performance of the embedded vision system. In this paper, we propose an improved method of image matching algorithms on vision system. We implement this architecture by FPGA, taking into account the techniques such as pipelining, parallel computing and distributed arithmetic. Experimental results show that our design achieve high speeds and provide low latency in vision system.
FPGA pipelining template matching distributed arithmetic real-time
SHEN Xiaolin
School of Information and Communication Engineering, North University of China, Taiyuan, 030051
国际会议
北京
英文
2007-08-05(万方平台首次上网日期,不代表论文的发表时间)