Design of the Pipeline Architecture High Speed Data Acquisition System Based on PCI Bus

摘要：

At present, more of the high speed data acquisition systems based on PCI bus are composed of high speed A/D converters, CPLD or FPGA, FIFO or dual-port SRAM and all-purpose PCI interface, they have bad versatility and flexibility, and cannot bring the performance of PCI bus into play well . Aiming at these insufficiencies, on the base of analysis for the characteristics of pipeline technology, a method for design the pipeline architecture high speed data acquisition system based on PCI bus is discussed. The data acquisition system designed according to this method not only can gain very high data acquisition speed and data transfer speed, but also has good versatility and flexibility.

关键词： PCI bus pipeline time parallel high speed data acquisition system

作者: MI Gensuo WANG Ruifeng

作者单位: School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou, 730070

会议类型: 国际会议

会议名称: 第七届国际测试技术研讨会

会议地点: 北京

会议语种:英文

在线出版日期: 2007-08-05（万方平台首次上网日期，不代表论文的发表时间）