Back-end Design and Implementation of a Low Power Grating Precision Measurement SoC
The back-end design and implementation of a low power grating precision measurement system chip EYAS is presented in this paper, which based on SVP and considering the interconnect effects in deep-submicron technology. With focus on the routing, analysis and iteration verification are carries out timely. Analog IP and an improved mixed signal back-end flow are used to run the co-design between analog part and digital part, ensuring the continuous convergence and manufacturability under timing driven. EYAS is taped out with HITC 0.18μm technology and passes the board level test successfully. It can work at 10 MHz with 1.25MHz sampling rate for orthogonal signals and the chip area is just 1.5×2.0mm2 after packaging. A grating precision angle/displacement measurement system has been built up taking EYAS as the controlling core and applied in the bore thread abrasion precision measurement of guns.
Grating Measurement System Mixed Signal Chip Physical Design Place & Route Iteration
WANG Wei LIU Cheng HOU Ligang ZHANG Jian WU Wuchen
VLSI & System Laboratory, Beijing University of Technology, Beijing, 100022
国际会议
北京
英文
2007-08-05（万方平台首次上网日期，不代表论文的发表时间）