The Study of the Parallel SOPC Architecture for High-speed Vision Measurement System

摘要：

A parallel SOPC (System On Programmable Chip) architecture used for high-speed vision measurement system is discussed in this paper. The advantage of parallel hardware method for high-speed image processing is analyzed, and working routes of measurement system applying SOPC as sub-module is introduced. The parallel SOPC architecture based on FPGA is described. The embedded processor, DSP model, special IPs (Intelligent Property), several custom logic models are included in a single FPGA. All units are seamlessly integrated into the overall system using the system builder interface. Different tasks are distributed to different units according to characteristics of image processing algorithms. Data exchange between units of SOPC is fulfilled by inside bus.

关键词： vision measurement SOPC FPGA image-processing algorithms

作者: LOU Xiaoping LV Naiguang DENG Wenyi NING Hui

作者单位: Department of Electronic Information Engineering, Beijing Institute of Machinery Beijing, China

会议类型: 国际会议

会议名称: 第七届国际测试技术研讨会

会议地点: 北京

会议语种:英文

在线出版日期: 2007-08-05（万方平台首次上网日期，不代表论文的发表时间）