A High-security and Low-power AES S-Box Full-custom Design for Wireless Sensor Network
The Advanced Encryption Standard (AES) S-Box was the only non-linear structure of the AES algorithm; it dominated the hardware complexity of the AES cryptographic module. For Wireless Sensor Network applications, S-Box must offer low power, small area and high security. In this paper, a full-custom S-Box implementation with low-power, compact and well DPAresistant property was proposed. The energy-efficient Pass Transmission Gate (PTG) and three-input exclusive-OR (XOR) gate based on three-transistor XOR element were used to realize the functionality of S-Box, it resulted in the reduction of the area tradeoff and power consumption. The PTG-based latches, controlled by asynchronous latch controllers, were inserted in the data path to block the propagation of the dynamic hazards. A countermeasure against Differential Power Analysis, based on random delay insertion, was presented to attain high-security. The resulting implementation on a 0.25μm CMOS process is very suitable for the source-limited wireless sensor node chips.
Advanced Encryption Standard (AES) Wireless Sensor Network S-Box Differentia Power Analysis asynchronous circuit random delay insertion
Liu Zhenglin Zeng Yonghong Zou Xuecheng Han Yu Chen Yicheng
Research Center for VLSI and Systems, Department of Electronic Science & Technology, Huazhong University of Science & Technology Wuhan 430074, China
国际会议
上海
英文
2007-09-21（万方平台首次上网日期，不代表论文的发表时间）