会议专题

Parallel Genetic Algorithm for VLSI Building Block Layout

The VLSI building block layout(BBL) becomes a more and more important problem for VLSI physical design. In this paper, A Multithread scheme for parallelizing a genetic algorithm for BBL placement optimization is presented. The parallel genetic algorithms(PGA) are realized, using sequence-pair(SP) as the representation. Parallel algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. Our experimental results on a SUN workstation with 4 CPUs have shown that the scheme is effective in improving performance of placement over that of a sequential implementation.

building block layout parallel genetic algorithms physical design

Ning Xu Feng Huang Zhonghua Jiang

Wuhan University of Technology,Wuhan 430070,China

国际会议

第二届IEEE无线通讯、网络技术暨移动计算国际会议

武汉

英文

2006-09-01(万方平台首次上网日期,不代表论文的发表时间)