VLSI Implementation of Karatsuba Algorithm and Its Evaluation

摘要：

VLSI implementation of Karatsuba algorithm for multi- digit multiplication was investigated. We designed 32-bit recursive Karatsuba multiplier (RKM) and found that its critical path delay and area cost are 9.44ns and 0.228mm<2>, respectively. Next we designed and evaluated RKM of larger bits. For bit length less than 2<9>, Wallace tree multiplier (WTM) has less area cost than RKM, while RKM has less area cost than WTM for bit length larger than 2<9>. The area cost of multiplier of 2<9> bits is approximately 30mm <2>. Critical path delay of RKM is always larger than that of WTM. We should use WTM instead of RKM as combinational circuits for iterative Karatsuba multiplier (IKM) to have better cost performance.

关键词： multi-digit multiplier Karatsuba VLSI

作者: Syunji Yazaki Koki Abe

作者单位: Department of Computer Science, The University of Electro-Communications, Chofu-shi,182-8585 Japan Department of Computer Science, The University of Electro-Communications, Chofu-shi, 182-8585 Japan

会议类型: 国际会议

会议名称: 2006现代科技国际研讨会(The International Workshop on Modern Science and Technology in 2006)

会议地点: 北京

会议语种:英文

页码: 378-383

在线出版日期: 2006-04-01（万方平台首次上网日期，不代表论文的发表时间）