A New Hierarchical Interconnection Network for Multi-Core Processor
On-chip communication architectures can have a great influence on the speed and area of multi-core processor (MCP) designs. A new chip design paradigm called Network-on-Chip (NOC) offers a promising interconnection architectural choice for future MCP. A new on-chip interconnection network named Triple-based Hierarchical Interconnection Network (THIN) is proposed that aims to decrease the node degree, reduce the links and shorten the diameter. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. THIN applies the hierarchical address-encoding scheme that can make the design of routing algorithm simple and efficient. The network properties are studied and compared with 2-D mesh. The results show that THIN is a better candidate for constructing the NOC than 2-D mesh, when there are not too many cores.
Baojun QIAO Feng SHI Weixing JI
School of Computer Science and Technology Beijing Institute of Technology,Beijing 100081 China; Inst School of Computer Science and Technology Beijing Institute of Technology,Beijing 100081 China
国际会议
2nd IEEE Conference on Industrial Electronics and Applications(ICIEA 2007)(第二届IEEE工业电子与应用国际会议)
哈尔滨
英文
2007-05-23（万方平台首次上网日期，不代表论文的发表时间）