Implementation of a ASIP for SELP Vocoder at Low Bit Rate of 600bps

摘要：

In this paper, efficient implementation of a 600bps SELP vocoder having a speech compression function used in the digital mobile communication is presented. This ASIP(Application Special Instruction set Processor) of vocoder is designed for high quality multi-rates speech coding algorithm based on SELP model. We adopt VLIW type instruction set and reconfigurable architecture, so those high complexity subprograms can be optimized to get a significant degree of instruction level parallelism. The result of simulation indicates that the algorithms implemented on this chip have higher efficiency than that on universal DSP, while maintaining the original coding quality. The presented chip can implement different kinds of speech coding algorithms and can achieve higher performance, lower complexity and lower cost.

作者: Tao JING Dahan HAN Qin WANG

作者单位: University of Science and Technology Beijing, China Tsinghua University, China

会议类型: 国际会议

会议名称: 2nd IEEE Conference on Industrial Electronics and Applications(ICIEA 2007)(第二届IEEE工业电子与应用国际会议)

会议地点: 哈尔滨

会议语种:英文

在线出版日期: 2007-05-23（万方平台首次上网日期，不代表论文的发表时间）