A Pipelined Interpolating Analog-to-Digital Converter with Reduced Nonlinearity Error

摘要：

An interpolating analog-to-digital converter (ADC) using pipelined architecture is designed. In order to obtain a high linearity of the ADC, a differential difference amplifier (DDA) with well restrained nonlinearity error is adopted to reduce the nonlinearity error. Furthermore, a latched comparator is proposed to achieve a low kickback noise, which is of great importance to the linearity of the ADC. The ADC is implemented in a 0.35μm standard digital CMOS process with a single 3.3V supply, and achieves 8bit resolution at speeds up to 50 Msamples/s.

作者: Xin ZHANG Dunshan YU Shimin SHENG

作者单位: Peking University, China

会议类型: 国际会议

会议名称: 2nd IEEE Conference on Industrial Electronics and Applications(ICIEA 2007)(第二届IEEE工业电子与应用国际会议)

会议地点: 哈尔滨

会议语种:英文

在线出版日期: 2007-05-23（万方平台首次上网日期，不代表论文的发表时间）