Research on Design for Testability of PCB Based on JTAG

摘要：

Design principle and methodology of DFT in BST are discussed,fault models of interconnect on a circuit board and equivalent exchange are done in order to simplify test process. Mathematical models of BST are established also in this thesis. Based on above principle and methodology, test stimuli generation and test response analysis of boundary scan interconnect test are studied. Two optimal boundary scan interlink age test algorithms are presented. Using DFT methodology of boundary scan, DFT of circuit board is finished, by two optimal algorithms, test effectiveness and correctness is validated.

关键词： Boundary scan design-for-Test PCB IEEE 1149.1 Standard

作者: Jia Hui Cai Xutao

作者单位: Naval Aeronautical Engineering Institute,Yantai 264001 China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）