Verification of AMBA Bus Model Using SystemVerilog

摘要：

A verification environment to verify an ARM-based SoC (System-on-Chip) by using SystemVerilog is presented in this paper. The new verification constructs can be easily reused for the objected-oriented feature of SystemVerilog. The paper also introduced how to design the AMBA (Advanced Microprocessors Bus Architecture) verification IP (Intellectual Property) by SystemVerilog, which include AHB (Advanced High Performance Bus) Master and AHB Monitor. The verification IP can be reused to verify any AMBA protocol based SoC. To reduce the time spending in the verification, a reference model designing method is also discussed in the paper.

关键词： SoC AMBA SystemVerilog Reference model Verification IP

作者: Han Ke Deng Zhongliang Shu Qiong

作者单位: School of Electronic Engineering,Beijing University of Posts and Telecommunications,Beijing 100876,C School of Electronic and Information Engineering,Beihang University,Beijing 100083,China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）