Design of SDRAM Controller in High-Speed Data Acquisition Based on PCI Bus

摘要：

To solve the problem of large capacity and high speed storage requirement in PCI high-speed data acquisition system(HDAS), a scheme of utilizing FPGA to realize the timing-logical control for the Synchronous DRAM (SDRAM), which is used as a data memory,is proposed. After analyzing the structural features of the SDRAM, the idea of design for SDRAM controller with Verilog HDL is given in detail. In the mean time, the FIFO technique is especially employed to solve the problem that SDRAM accessed by computer through PCI bus. Lastly, the correctness of the design is proved by the corresponding timing simulation.

关键词： High-speed Data Acquisition PCI Bus FPGA SDRAM Controller State Machine

作者: Qiu Daqiang Hu Bing Li Dandan

作者单位: School of Electrical and Information Engineering,Xihua University,Chengdu,610039,China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）