Research and Design for High-Speed, Real-time and Vast-Capacity Data Acquisition System
This paper shows a new design for data acquisition system in automobile engine analysis instrument. Having been compared with some schemes, the system is characteristic of automatism, high-speed, vast-capacity, and real-time. Through adopting ping-pong memory access to DSP and FPGA/CPLD, and setting four modes, the system controls two slices of SRAM to write and read the data converted from A/D alternately. In this way, A/D acquires data uninterruptedly while DSP reads and processes the sample data. Furthermore the data pretreated by DSP communicate with upper ARM using the HPI that has function of DMA. Accordingly, the system realizes parallel communication of collecting data, pretreating and transmitring, while solves the problems including of depth of buffer, DSP control and FPGA/CPLD status. In this paper, the logic structure of FPGA/ CPLD was designed using VHDL and was simulated and analyzed. The design and debug of soft interface was completed by applying C language of DSP, which supply the driver for the software design on apply layer.
The engine analysis instrument Data acquisition DSP CPLD Ping-Pong Memory Accesses
Cai Qizhong Chen Zhixin Wang Rugang Yuan Haiying Shi Lianwen
Guangxi University of Technology,Liuzhou 545006 China Beijing Institute of Civil Engineering and Architecture,Beijing 100044 China Shenzhen Pluke Intelligent Test Equipment Co.LTD,Shenzhen 518067 China
国际会议
西安
英文
2007-08-16（万方平台首次上网日期，不代表论文的发表时间）