A 16-Port Data Cache for Chip Multi-Processor Architecture

摘要：

With the development of the modern architecture and chip integration technology, parallel process technologies have become the mainstream. The increasingly large gap between processor and memory speed has made the design of high bandwidth and large scale cache a key part in high performance microprocessor. In this paper, we describe the design of a 16-port data cache, which is 8-way associative using Pseudo-LRU replacement policy. The interleaved storage and cross-switch interconnection techniques enable the cache can response for up to 16 concurrent access requests.

关键词： Chip Multi-Processor Multi-Port Data Cache Dual-Port RAM

作者: Wang Jing Fan Xiaoya Wang Hai Yang Ming

作者单位: Department of Computer Science,Northwestern Polytechnical University School of Mechanical engineering,Tongji University

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）