Path Delay Fault Design For Test and Testability Analysis of Conditional Sum Adders

摘要：

Conditional sum adders (CSA) are kinds of high-speed adders and the existing delay faults have crucial influence on their performance. Detail path delay fault testability analysis is proposed and a design-for-test scheme with low overhead and low size of test set is presented which can guarantee single path propagating hazard-free fully robust path delay fault testability of CSA. This is the strictest requirement for path delay fault testing. Based on the scheme, a test set of minimal size is derived by exploiting its structural property and parallel testing.

关键词： design-for-test path delay fault test

作者: Yang Decai Chen Guangju Xie Yongle

作者单位: College of Automation,University of Electronic Science and Technology of China,Chengdu,610054 China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）