An Adjustable Clock Scan Structure for Reducing Testing Peak Power

摘要：

Power consumption during testing is becoming a primary concern. In this paper, an adjustable clock scan structure is presented. It can significantly reduce the peak power consumption during testing. The adjustable clock controlling multiple scan chains is used to reduce SA (switching activity) and avoid simultaneous shifting operation. Compared with exiting techniques of low power scan testing, the adjustable clock scan structure has numerous advantages. It keeps peak power below a limit and maintains the same fault coverage. Moreover, it only takes up small DFT hardwires. Theoretical analysis and experiments on ISCAS89 benchmark circuits conformably show that the peak power consumption is reduced by about 60％ during testing.

关键词： Design for testability fault coverage peak power consumption circuits under test

作者: Zhang Jinyi Zhang Tianbao Yun Feng Gui Jianghua

作者单位: Key Laboratory of Advanced Display and System Applications (Shanghai University),Ministry of Education Microelectronic Research & Development Center,Shanghai University Shanghai 200072,China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）