A Digital Phase-locked Loop Based on MAP in PLC

摘要：

The conventional DPLLs (Digital Phase-locked Loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced Class A noise model in PLC first, and then proposed an optimum DPLL for such Class A noise environment using the techniques based on MAP (Maximum A Posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under Class A noise environment.

关键词： power line communication impulsive noise max a posteriori digital phased-locked loop

作者: Lu Saijun Li Qianshu Mao Taiping

作者单位: Institute of Intelligent Information Processing,Guizhou Normal University,.Guiyang 550001 Center for Scientific Computation,Guiyang,550001

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）