FPGA-based Digital Phase-Sensitive Demodulator for EIT System

摘要：

Electrical Impedance Tomography(EIT)requires high precision voltage measurement to reconstruct image.In this paper a novel FPGA-based digital phase-sensitive demodulator designed for EIT system is put forward.Unlike the traditional analog multiplier demodulator of poor dynamic behavior and high noise,the digital demodulation is used to obtain both in-phase and quadrature components of the voltage signal with high SNR,high data precision and high demodulation speed.This paper first expounds the theory of digital phase-sensitive demodulator,then discusses the blocks and technique specification of the demodulator.Different parts are realized by VHDL.The demodulator is implemented and tested.Emulation is given by QUARTUS II and the phase error is 1.03°.The result shows that the digital demodulator is suitable for the signal processing in EIT system and meets the requirement of digitized EIT system.

关键词： EIT FPGA Digital Phase-Sensitive Demodulator A/D sampling

作者: Kou Ge Rong Lifeng

作者单位: School of Electronic Engineering and Optoelectronic Technology,Nanjing University of Science &Technology,Nanjing,210094 China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）