Implementation of High-speed High-resolution Data Conversion System Using FPGA

摘要：

This paper analyzes the implementation of high-speed high-resolution data conversion system based on Subranging A/D model in detail. We use a 10 bit ADC and an 8 bit ADC to construct the Subranging A/D system and then make a simulation by QuartusII. The result of the experiment shows that the systems sampling rates is 17MHz, and the resolution is 16 bit, so it can solve an antinomy between sampling rates and resolution, which is prevalent in current market.

关键词： High-speed High-resolution ADC FPGA

作者: Cao Xiaoqiu Zeng Jin Yang Tao

作者单位: College of Electronic and Control Engineering of Beijing University of Technology,Beijing 100022 China

会议类型: 国际会议

会议名称: 第八届国际电子测量与仪器学术会议(Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments)

会议地点: 西安

会议语种:英文

在线出版日期: 2007-08-16（万方平台首次上网日期，不代表论文的发表时间）